Gate Capacitances Behavior of Nanometer FD SOI CMOS Devices With HfO2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects Using 2-D Simulation [Електронний ресурс] / Y.-S. Lin, C.-H. Lin, J. B. Kuo, K.-W. Su // IEEE Transactions on Electron Devices. – 2006. – № 6. – P. 1373–1378
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Статистика використання: Завантажень: 2
Анотація:
This paper reports the gate–source (drain)/source (drain)–gate capacitance behavior of 100-nm fully depleted silicon-on-insulator CMOS devices with HfO2 high-k gate dielectric
considering vertical and fringing displacement effects. Based on the two-dimensional simulation results, a unique two-step CS(D)G/CGS versus VG curve could be identified for the device with the 1.5-nm HfO2 gate dielectric due to the vertical and fringing displacement effects.
considering vertical and fringing displacement effects. Based on the two-dimensional simulation results, a unique two-step CS(D)G/CGS versus VG curve could be identified for the device with the 1.5-nm HfO2 gate dielectric due to the vertical and fringing displacement effects.