Wang J.-P. Device Enhancement Using Process-Strained-Si for sub-100-nm nMOSFET [Електронний ресурс] / J.-P. Wang, Y.-K. Su, J. F. Chen // IEEE Transactions on Electron Devices. – 2006. – № 5. – P. 1276–1279
- Електронна версія (pdf / 185 Kb)
Статистика використання: Завантажень: 1
Анотація:
Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6 мm for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917 мA/мm for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.
Тема: