Surface channel strained-silicon MOSFETs on relaxed Si1.xGex virtual substrates (VSs) have been established as an attractive avenue for extending Si CMOS performance as
dictated by Moore’s law. The performance of a surface channel Si n-MOSFET is significantly influenced by strained Si/SiO2 interface quality. The effects of Ge content (20, 25, and 30%) in the VS and strained-Si thickness (6, 5.5, 4.7, and 3.7 nm) on the strained Si/SiO2 interface have been investigated. The interface trap density was found to be proportional to the Ge content in the VS. Fixed oxide charge density reduces to a lower limit at higher strained-Si thickness for any Ge content in the VS, and the value increases as the strained-Si thickness is reduced. There is a high concentration of interface trap charge and fixed oxide charge present for devices with a strained-Si channel thickness below 4.7 nm. To investigate the effect of strained Si/SiO2 interface quality on MOSFET devices fabricated using a hightemperature CMOS proces