In this paper, the metal source/drain (S/D) Schottkybarrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate
lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic
Schottky potential barrier, and elimination of parasitic bipolar action. These and other benefits accrue using a lowthermal-budget CMOS manufacturing process requiring two
fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials such as high-k gate insulators and strained silicon substrates. SB MOSFET technology state of the art is also reviewed, and shown
to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region. SB-PMOS devices tend to h