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Performance Enhancement of Partially and Fully Depleted Strained-SOI MOSFETs [Електронний ресурс] / Toshinori Numata, Toshifumi Irisawa, Tsutomu Tezuka и др. // IEEE Transactions on Electron Devices. – 2006. – № 5. – P. 1030–1038


Статистика використання: Завантажень: 1
Анотація:
The authors have developed short-channel strained-silicon-on-insulator (strained-SOI) MOSFETs on silicon–germanium (SiGe)-on-insulator (SGOI) substrates fabricated by the Ge condensation technique. 35-nm-gate-length strained- SOI MOSFETs were successfully fabricated. The strain in Si channel is still maintained for the gate length of 35 nm. The performance enhancement of over 15% was obtained in 70-nm-gatelength strained-SOI n-MOSFETs. Fully depleted strained-SOI MOSFETs with back gate were successfully fabricated on SGOI substrate with SiGe layers as thin as 25 nm. The back-gate bias control successfully operated and the higher current drive was obtained by a combination of the low doping channel and the back-gate control.