Issues surrounding the integration of Hf-based high-к dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as
well as optimization of other CMOS process steps enable robust metal/high-к CMOSFETs with wide process latitude. HfO2 of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A hightemperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-к stack, integrating
two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and g