The aim of the certification work was development of verification methodology of VHDL-models. The feature of this methodology is usage of formal and test approaches. As for test stage is necessary execution of simulation process (compilation, elaboration, simulation) that it requires some shell of model testing. This shell is creating by software module. The work contains review of traditional verification methods, detailed description of developed methodology and practical application this methodology on the example of asynchronous memory verification.
The developed methodology can be used for verification of VHDL-models with different description levels (behavioral, structural)

VERIFICATION, FORMAL VERIFICATION, TEST VERIFICATION, VERIFICATION METHODS, SIMULATION, SPECIFICATION