ЕОМ
Богдан П. І. Нейроконтролер на базі віртуального нейропроцесора : магістерська атестаційна робота, пояснювальна записка / П. І. Богдан ; кер. роботи проф. Руденко О.Г. ; ХНУРЕ, Кафедра Електронних обчислювальних машин. – Харків, 2014. – 69 с. : CD
Богдан П. І. Нейроконтролер на базі віртуального нейропроцесора : магістерська атестаційна робота, пояснювальна записка / П. І. Богдан ; кер. роботи проф. Руденко О.Г. ; ХНУРЕ, Кафедра Електронних обчислювальних машин. – Харків, 2014. – 69 с. : CD
Статистика використання: Видач: 0
Анотація:
The purpose of the degree project is development of hardware-software device of analyzing of digital signals in analog and digital systems. Sensors for processing and the further logic analyzing of digital signals are picked up. On the basis of the analysis of the information the hardware and software were developed. FPGA for the logic analyzer was chosen, the basic schematic is developed and the software for management of this system is created.
MICROCONTROLLER, PROCESSOR, KERNEL, FPGA, DIGITAL AUTOMATIC DEVICE, CONTROL SYSTEM, MEASUREMENT, MICROCONTROLLER SYSTEM, SYSTEM of PROCESSING of the INFORMATION, PULSE-WIDTH MODULATION, INTERFACE
This work dedicates the syntesis of arithmetical conveyor that realizes one neuroprocessors. There were viewed some questions of command choicing for specialized neurocomputers, one algorithm of command was proposed and generalized scheme of arithmetical conveyor was described.
The structural schemes of neurocontrol and arithmetical conveyor were researched and analyzed and the realization of neuroconveyor based on FPGA 1802 was described .
NEUROPROCESSOR, NEUROCHIP, ARITHMETIC PIPELINE, ALGORITHM, STRUCTURE OF INSTRUCTIONS, STRUCTURE CHART
MICROCONTROLLER, PROCESSOR, KERNEL, FPGA, DIGITAL AUTOMATIC DEVICE, CONTROL SYSTEM, MEASUREMENT, MICROCONTROLLER SYSTEM, SYSTEM of PROCESSING of the INFORMATION, PULSE-WIDTH MODULATION, INTERFACE
This work dedicates the syntesis of arithmetical conveyor that realizes one neuroprocessors. There were viewed some questions of command choicing for specialized neurocomputers, one algorithm of command was proposed and generalized scheme of arithmetical conveyor was described.
The structural schemes of neurocontrol and arithmetical conveyor were researched and analyzed and the realization of neuroconveyor based on FPGA 1802 was described .
NEUROPROCESSOR, NEUROCHIP, ARITHMETIC PIPELINE, ALGORITHM, STRUCTURE OF INSTRUCTIONS, STRUCTURE CHART